Optical DUV (deep ultraviolet, 193 nm) immersion lithography with NA≈1.3 has the capability of printing half-pitch features down to about 40 nm. The potential next-generation lithography (NGL) technologies include EUV (extreme ultraviolet), maskless, and nano-imprint lithography [1]. However, all these NGL technologies face their own technological challenges and still need a long development time before their applications in high-throughput manufacturing. Recently, double patterning has attracted much industrial interest which prints less dense line/space or contact hole patterns twice on the same wafer to finally obtain dense patterns with double spatial frequency [2]. In principle, a similar multiple-patterning concept can be developed but both need extremely high alignment accuracy. It is a severe challenge to significantly reduce the misalignment budget in a lithographic process to meet the multiple-patterning requirement at 32 nm half pitch and below. Therefore, post-lithography misalignment correction will be a promising alternative technology enabling multiple patterning (including double patterning) for future semiconductor manufacturing. It provides a production-worthy method for the whole semiconductor industry to continue device scaling beyond sub-40 nm generation with no need of NGL technology.
Several post-lithography misalignment correction techniques based on the shadow effect in anisotropic plasma etch or sputtering/evaporation processes are invented which allow us to significantly reduce the misalignment created in a lithographic process. Next, we demonstrate the forming mechanism of misaligned dense line/space patterns during a double-patterning process. Similar misalignment mechanism exists in the multiple-patterning process.
In FIG. 1, the cross-section view of a double-patterning process flow to print misaligned dense line/space and contact hole patterns is shown. Starting with a targeted layer on top of the substrate, semi-dense features are printed on the targeted layer using standard lithographic and dry etching processes (shown in FIG. 1(B)), with their pitch size twice the size of desired pitch as shown in FIG. 1 (E). After that, another resist film is spun on the top and the wafer is exposed again with the same pattern shifted by a distance such that ideally every trench center in the resist will be coincident with the center of corresponding line structure underneath. However, as shown in FIG. 1(C), the trench is not located right at the center of the line (e.g., A≠B) due to an unavoidable misalignment during a lithographic process. Consequently, this misalignment will be transferred to the targeted layer underneath in the following plasma etching process assuming its etching direction is vertical as shown in FIG. 1(D). This results in unequal width of the final dense features (e.g., length C≠D) and brings serious challenges to process yield and circuit design/layout. Similar problem exists in a multiple-patterning process to obtain dense features with their pitch reduced to ⅓, ¼, . . . , of the original size corresponding to the resolution limit of a conventional lithographic tool.
The process flow shown in FIG. 2 is similar to previously described process except that a sacrificial layer is deposited before the second lithographic step. This sacrificial layer finally will be released and can be polished to flatten the surface (e.g., with a CMP process) resulting in an improved lithographic process window. However, if the plasma etching direction is vertical, the misalignment is still transferred to the targeted layer as shown in FIG. 2(F) (e.g., C≠D).
As demonstrated before, if the ions' incident direction is vertical to the substrate surface, the misalignment will be transferred to the targeted layer. Next, we shall describe a so-called shadow effect which occurs in both subtractive anisotropic plasma etching and additive sputtering/evaporation processes, and can be used to correct the misalignment created during a lithographic process. As shown in FIG. 3, we compare two plasma etching processes in which one etching is in vertical direction as shown in FIG. 3(A), and the other etching is tilted by certain angle as shown in FIG. 3(B). The tilted etching can be achieved by either directly tilting the ions' bombarding direction or tilting the wafer surface. Both dash lines drawn in the figure represent the central position of the right-side structure formed in a vertical etching process. When the etching direction is tilted as shown in FIG. 3(B), two effects occur. First, the slope of left side walls of the etched structures becomes more vertical while the opposite happens to the slope of right side walls, which results in asymmetric final structures. Secondly, relative to the dashed line which indicates the center of a final structure produced in the vertical etching, the mass center of the asymmetric structure formed in a tilted etching process moves toward the right side. The shift distance depends on the etching direction as well as the etching selectivity. Even though the etched structures are asymmetric, this asymmetry will not be transferred to the substrate if we can use those structures as a hard mask with high selectivity when etching the underneath substrate.
The shadow effect also occurs in an additive process such as sputtering or evaporation deposition as shown in FIG. 4. First, a dense structure is patterned and etched into the substrate. When the sputtering direction is tilted toward the right side, the step coverage is not conformal as deposition occurs only on the top and left side walls. This effect can also be used to correct misalignment.
The misalignment correction process can vary, depending on whether a sacrificial layer is used between two exposures (e.g., in a double-patterning process) and when the misalignment can be measured. We shall demonstrate the correction processes based on the shadow effect of anisotropic plasma etching without a sacrificial layer first.